Ultra - smooth platinum surfaces for nanoscale devices fabricated using chemical mechanical polishing

A technique involving two steps of chemical mechanical polishing (CMP) has been developed to produce ultra-smooth metal surfaces with an RMS roughness better than 0.1 nm. A figure of merit termed degree of smoothness (DOS) is proposed for the purpose of quantifying the extent of smoothness of a polished metal surface. A post CMP metal slurry cleaning solution was used for cleaning Pt slurry for the first time and by applying special techniques, a very high quality clean surface was attained. Applications of the polished Pt electrodes in interfacing molecular switching devices with self-assembled monolayers of molecules have been found to dramatically improve the packing and orientation of the molecular monolayer with a huge improvement in the molecular electronics device yields. These smooth metal surfaces may open doors for new opportunities in future nanoscale devices. 1 Introduction Chemical mechanical polishing (CMP), first introduced into the semiconductor industry to planarize interlevel dielectrics (ILD), has been very effective in implementing multi-level metallization integration [1]. New techniques and consumables for polishing copper (Cu), tungsten (W) and shallow trench isolation (STI) have revolutionized semiconductor manufacturing [1–9]. Although the process was initially developed for ILD, it began to be used instead of reactive ion etching (RIE) to remove tungsten that was deposited to fill the via opening between metal layers [10]. Over time, the fabrication of inlaid trenches filled with metal, also known as damascene, was developed. All these eventually led to copper interconnects in standard semiconductor processing. Without CMP, Cu could have not been used for interconnects even though it has lower resistivity than aluminum (Al) due to difficulty of etching Cu with RIE. The CMP process for conventional microelectronics industry has experienced an ongoing development over several years and a great deal has been accomplished in terms of precise control of removal rate, surface smoothness, reduced micro-scratches, local and global uniformity. Although feature sizes are shrinking to diminishing dimensions, the devices and interconnects in a microprocessor or memory array are much larger than the residual surface roughness that an optimum CMP process can offer today. However, as the device feature size further decreases and research community looks for alternative materials for electronic devices, such as DNA, organic molecules or carbon nanotubes, the requirement for CMP is going to be more stringent and the traditional CMP process will need to go through enormous improvements to be applicable in the fabrication of nanode-vices. New types …